Xilinx to bring analog conversion onto finFET FPGAs
Xilinx plans to add high-speed analog interfaces to its upcoming field-programmable gate arrays (FPGAs) to better support high-density 5G basestation designs. The decision follows an extensive R&D...
View ArticlePOSTPONED: Get to grips with new PC, monitor energy regs
PLEASE NOTE THIS EVENT HAS BEEN POSTPONED. The Electronic System Design Alliance (formerly the EDA Consortium) has postponed its panel discussion originally scheduled for later this month in San Jose...
View ArticleSonics adds heat-aware DVFS to SoC power controller
Sonics has developed a version of its power-management IP core for SoCs that adds support for dynamic voltage and frequency scaling (DVFS), along with the ability to tune settings according to...
View ArticleMCU benchmark homes in on peripheral power
The EEMBC benchmarking consortium has released the latest in its collection of test suites for measuring power efficiency in embedded microcontrollers, focusing in this case on peripheral performance....
View ArticleLearn how to simplify power states in UPF
The latest edition of the Unified Power Format (UPF – IEEE 1801) low-power verification methodology addresses a recently growing concern with the definition of power states. Mentor, a Siemens business,...
View ArticleAI is all about low-energy hardware says Dally
For nVidia chief scientist and Stanford professor Bill Dally, now is a great time to be involved in hardware design. The rapid growth of machine learning as part of a push towards artificial...
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IEDM shows progress on embedded eMRAM
Embedded magnetic RAM is emerging as a contender for on-chip memory not just from a density standpoint but from that of power. In his presentation during the plenary at this year’s International...
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Low-power pioneer to receive 2019 Kaufman Award
Dr Mary Jane Irwin of Penn State University has been named as the first female recipient of the Phil Kaufman Award for distinguished contributions to electronic system design. Dr Irwin is the Evan Pugh...
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Master the design and verification of next gen transport: Part Two –...
Part one of this series outlined advantages of high-level synthesis (HLS) and emulation that next generation transportation designs can exploit. This second part goes into more detail as to how...
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Nanometer scaling puts focus on power at VLSI in June
At the upcoming Symposia on VLSI Technology & Circuits, the first to be held online, engineers from Qualcomm will describe an adaptive clocking scheme to cope with short-term power fluctuations and...
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