Cadence ties IR drop into static timing analysis
Cadence Design Systems claims to have closed the loop between static timing and IC-level power-integrity analysis with the launch of its Voltus tool. The software deploys parallelism to speed up...
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Qualcomm’s take on preserving Moore’s Law economics
Qualcomm’s VP of Technology does not share the same concerns as some of his colleagues as 20nm. However, as Geoffrey Yeap told IEDM 2013 in a keynote address, he is still concerned about what will...
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TSMC hints at glass interposer for mobile SoCs
Once upon a time, the interposer was seen as something of an interim technology, a stopping-off point on the way to through-silicon-via 3D stacks. But that isn’t stopping TSMC continuing to invest in...
View ArticleIEA takes aim at network-device energy consumption
Taking the experience with cutting the standby power consumption of consumer electronics items such as TVs as an example of successful lobbying, the International Energy Agency (IEA) has now turned its...
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ARM explores multithreaded core as alternative to GPU computing
ARM is working on a heavily multithreaded version of its processor core to see if it can provide a more convenient alternative to graphics processing units (GPUs) for heterogeneous computing, CTO Mike...
View ArticleNew flows needed for the ‘insects of the SoC world’
Chris Rowen, CTO of the IP group at Cadence Design Systems, expects the internet of things (IoT) to cause a split in approaches to SoC design, one of a set of predictions he has made about a movement...
View ArticleTSMC adds sub-micron low-leakage processes
TSMC has launched three processes the foundry is aiming at internet-of-things (IoT) and wearable-device designs, providing lower-leakage versions of its 55nm, 40nm and 28nm processes. The new processes...
View ArticleThe changes demanded by IoT design
Does the internet of things (IoT) require a change in design techniques? A number of people involved in the EDA industry reckon it does, partly because it could seed a much richer variety of SoC design...
View ArticleARM puts IoT operating system on roadmap in software drive
ARM is making a free operating system a cornerstone of its push into selling both more cores and server software to help manage them. But the company has yet to clarify how it will implement key...
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ARM to extend Big.Little for GPUs and heat management
A multiprocessor test chip has led ARM to improve the energy-control strategy for its Big.Little architecture and to simplify the debug architecture for the company’s multicore processor IP. Launched...
View ArticleAmbiq uses subthreshold techniques to cut power on ARM MCUs
Research by the University of Michigan into subthreshold circuit design has led to spinoff company Ambiq Micro creating a family of microcontrollers that it claims provide an ARM Cortex-M4F with power...
View ArticleCea-Leti opens FD-SOI design center
CEA-Leti has launched a design center called Silicon Impulse with the intention of lowering the entry barrier to using the FD-SOI process. Olivier Thomas, CEA-Leti design center project leader, said:...
View ArticleTI uses Cortex-M4F to provide low-power 32bit upgrade for MSP430
Texas Instruments has launched a family of ARM-based microcontrollers intended to act as a migration path from its low-energy 16bit MSP430 series, developing its own flash-capable 90nm process to...
View ArticleFusion core targets voice-activated devices
Cadence Design Systems has launched a processor core aimed at ‘always on’ signal-processing applications such as voice detection and recognition for wearables. The company has derived the Tensilica...
View ArticleEEMBC starts work on IoT-node power benchmark
Benchmarking organization EEMBC has kicked off an effort to develop a set of performance tests for edge nodes for the Internet of Things (IoT). Focus on the energy efficiency of edge nodes, the...
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Sonics readies fine-grained power-gating architecture
On-chip networks specialist Sonics is extending into power management with an approach intended to substantially automate much of the job of building finely grained power-gated SoCs. The ICE-Grain...
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Mentor zooms in on power peaks with emulator interface
Mentor Graphics has developed a software interface for its Veloce emulators that lets third-party tools fetch logic-activity information from running tasks for faster and more accurate power...
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Cadence deploys parallel strategy for faster synthesis
RTL synthesis has joined the array of tools developed by Cadence Design Systems that employ distributed processing, with the aim of exploring more ways of creating area- and power-efficient logic...
View ArticleDocea adds API to model power software interactions
Docea Power has added a programming interface to the latest version of its Aceplorer power-modeling software to let engineering teams see how chipset designs would fare under a variety of...
View ArticleSynopsys to acquire Atrenta
Synopsys is to acquire rival vendor Atrenta in another major consolidation of the EDA tools market. The deal was announced late on Sunday (June 7) ahead of the opening day of the 2015 Design Automation...
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